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|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 8 channel i2c bus multiple xer with reset 2 0 1 5 - 0 7 - 0 0 4 0 pt054 4 - 2 8 / 1 8 /1 5 1 PI4MSD5V9547 features ? 1 - of - 8 bidirectional translating multiplexer ? i2c - bus interface logic ? operating p ower supply voltage from 1.6 5 v to 5.5 v ? allows voltage level translation between 1.2v, 1.8v,2 .5 v, 3.3 v and 5 v buses ? low standby current ? low ron switches ? active low r eset input ? channel selection via i2c bus ? power - up with one channel on ? capacitance isolation when channel disabled ? no glitch on power - up ? supports hot insertion ? 5 v tolerant inputs ? 0 hz to 400 khz clock frequency ? esd protection exceeds 8 000 v hbm per jesd2 2 - a114, and 1000 v cdm per jesd22 - c101 ? latch - up testing is done to jedec standard jesd78 which exceeds 100 ma ? packages offered: ts sop - 24l ,t q fn - 24zd pin configuration description the PI4MSD5V9547 is an octal bidirectional translating multiplexer controlled by the i2c - bus. the scl/sda upstream pair fans out to eight downstream pairs, or channels. only one scx/sdx channel can be selected at a time, determined by the contents of the prog rammable control register. the device powers up with channel 0 connected, allowing immediate communication between the master and downstream devices on that channel. an active low reset input allows the PI4MSD5V9547 to recover from a situation where one of the downstream i2c - buses is stuck in a low state. pulling the reset pin low resets the i2c - bus state machine and causes all the channels to be deselected as does the internal power - on reset (por) function. the pass gates of the switches are constructed su ch that the vcc pin can be used to limit the maximum high voltage which is passed by the PI4MSD5V9547 . this allows the use of different bus voltages on each pair, so that 1.2v, 1.8 v or 2.5 v or 3.3 v parts can communicate with 5 v parts without any additio nal protection. external pull - up resistors pull the bus up to the desired voltage level for each channel. all i/o pins are 5 v tolerant. tssop t q fn
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 8 channel i2c bus multiple xer with reset 2 0 1 5 - 0 7 - 0 0 4 0 pt054 4 - 2 8 / 1 8 /1 5 2 PI4MSD5V9547 pin description pin no . (tssop, soic) pin no . (tqfn) pin name type de scription 1 22 a0 i address input 0 2 23 a1 i address input 1 3 24 i active low reset input 4 1 sd0 i/o serial data 0 5 2 sc0 i/o serial clock 0 6 3 sd1 i/o serial data 1 7 4 sc1 i/o serial clock 1 8 5 sd2 i/o serial data 2 9 6 sc2 i/o serial cl ock 2 10 7 sd3 i/o serial data 3 11 8 sc3 i/o serial clock 3 12 9 gnd ground supply ground 13 10 sd4 i/o serial data 4 14 11 sc4 i/o serial clock 4 15 12 sd5 i/o serial data 5 16 13 sc5 i/o serial clock 5 17 14 sd6 i/o serial data 6 18 15 sc6 i/o serial clock 6 19 16 sd7 i/o serial data 7 20 17 sc7 i/o serial clock 7 21 18 a2 i address input 2 22 19 scl i/o serial clock line 23 20 sda i/o serial data line 24 21 vcc power supply voltage reset t
|||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 4 0 pt054 4 - 2 8 / 1 8 /1 5 3 pi4 msd5v954 7 8 channel i2c bus multiplexer with reset block diagram figure 1: block diagram maximum rating s storage temperature .............. .......................... ......... C 5 5c to +1 25 c supply voltage port b ...... ......................................... .. C 0.5v to + 6.0 v supply voltage port a ........ ........................................ C 0.5v to + 6.0 v dc input voltage ......................... .............................. C 0.5v to +6 .0 v control input voltage (en ) ...... ..................... ....... C 0.5v to +6 .0 v t otal power dissipation (1) ............. ...................................... .... 10 0mw i nput current (en,vcc , gnd) .............. ................... .... 50ma esd: hbm mode ............. ................................................. ....... 8000v recommended operation conditions symbol parameter min typ max unit v cc v cca positive dc suppl y voltage 1.65 - 5.5 v v en enable control pin voltage gnd - 5.5 v v io i/o pin voltage gnd - 5.5 v t /v input transition rise or fall time - - 10 ns/v t a operating temperature range ? 40 - +85 c note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only a nd functional operation of the device at these or any other condi - tions above those indicated in the operational sec - tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
|||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 4 0 pt054 4 - 2 8 / 1 8 /1 5 4 pi4 msd5v954 7 8 channel i2c bus multiplexer with reset dc electrical characteristics unless otherwise spec ified, - 40ct a 8 5c , 1. 1 v vcc 3.6 v symbol parameter conditions vcc min typ max unit supply vcc supply voltage 1.65 5.5 v icc supply current operating mode; no load; v i = vcc or gnd; fscl = 100 khz 3.6v to 5.5v 65 100 ua 2.3v to 3.6v 2 0 50 ua 1.65v to 2.3v 10 30 ua istb standby current standby mode; vcc = 3.6 v; no load; v i = vcc or gnd; fscl = 0 khz 3.6v to 5.5v 0. 3 1 ua 2.3v to 3.6v 0. 1 1 ua 1.65v to 2.3v 0.1 1 ua vpor [1] power - on reset voltage no load; v i = vcc o r gnd 3.6v to 5.5v 1.3 1.5 v input scl; input/output sda v il low - level input voltage 1.65v to 5.5v - 0.5 +0.3 vcc v v ih high - level input voltage 1.65v to 2v 0.75 vcc 6 v 2v to 5.5v 0.7 vcc 6 v i ol low - level output current v ol = 0.4 v 1.65v to 5.5 v 3 - ma v ol = 0.6 v 1.65v to 5.5v 6 - ma i il low - level input current v i = gnd 1.65v to 5.5v - 1 +1 ua i ih high - level input current v i = vcc 1.65v to 5.5v - 1 +1 ua ci input capacitance vi = gnd 1.65v to 5.5v - 1 4 19 pf select inputs a0, a 1 , a2,reset v il low - level input voltage 1.65v to 5.5v - 0.5 +0.3 vcc v v ih high - level input voltage 1.65v to 5.5v 0.7 vcc 6 v i il low - level input current v i = gnd 1.65v to 5.5v - 1 +1 ua ci input capacitance v i = gnd 1.65 v to 5.5v 3 5 pf pass ga te ron on - state resistance v o = 0.4 v; i o = 15 ma 4.5 v to 5.5 v 4 9 24 o = 0.4 v; i o = 10ma 2.3v to 2.7v 7 16 55 l leakage current vi = vcc or gnd 1.65v to 5.5v - 1 +1 ua cio input/output capacitance vi = vcc or gnd 1 .65v to 5.5v 3 5 pf note : [1] vcc must be lowered to 0.2 v for at least 5 u s in order to reset part.
|||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 4 0 pt054 4 - 2 8 / 1 8 /1 5 5 pi4 msd5v954 7 8 channel i2c bus multiplexer with reset ac electrical characteristics tamb = - 40 o c to +85 o c; unless otherwise specified. symbol parameter conditions vcc min typ max unit t pd [1] propaga tion delay f rom sda to sdx, or scl to scx 1.65v to 5.5v 0.3 ns reset t w(rst)l low - level reset time 1.65v to 5.5v 4 ns t rst reset time sda clear 1.65v to 5.5v 500 ns t rec;sta recovery time to start condition 1.65v to 5.5v 0 ns note [1] pass g ate propagation delay is calculated from the 20 typical ron and the 15 pf load capacitance. i2c interface timing requirements symbol parameter standard mode i 2 c bus fast mode i 2 c bus unit min max min max fscl i2c clock frequency 0 100 0 400 khz t low i2c clock high time 4.7 1.3 s high i2 c clock low time 4 0.6 s sp i2c spike time 50 50 ns t su:dat i2c serial - data setup time 250 100 ns t hd :dat i2c serial - data hold time 0 [1] 0 [1] s buf i2c bus free time between stop and start 4.7 1.3 s su:sta i2c start or repeated start condition setup 4.7 0.6 s hd:sta i2c start or repeated start condition hold 4 0.6 s su:sto i2c stop condition setup 4 0.6 s vd:dat valid - data time (high to low) [ 2 ] scl low to sda output low valid 1 1 s [ 2 ] scl low to sda output high valid 0.6 0.6 s vd:ack valid - data time of ack condition ack signal from scl low to sda output low 1 1 s notes: [1] a device internally must provide a hold time of at least 300 ns for the sda signal (referred to as the vih min of the scl signal), in order to bridge the undefined region of the falling edge of scl. [ 2 ] data taken using a 1 - k? pul l up resistor and 50 - pf load notes
|||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 4 0 pt054 4 - 2 8 / 1 8 /1 5 6 pi4 msd5v954 7 8 channel i2c bus multiplexer with reset figure 2 . definition of timing on the i2c - bus application figure 3 . typical application recommended application voltage condition vcc vpu1 vpu2 1.8v 1. 5 v - 5.5v 1.2v - 5.5v 2.5v 1.8 v - 5.5v 1.8v - 5.5v 3.3v 2.7 v - 5.5v 2.7v - 5.5v 5v 4.5v - 5.5v 4.5v - 5.5v
|||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 4 0 pt054 4 - 2 8 / 1 8 /1 5 7 pi4 msd5v954 7 8 channel i2c bus multiplexer with reset device addressing following a start condition the bus master must output the address of the slave it is accessing. the address of the PI4MSD5V9547 is shown in figure 4 . the last bit of the slave address defines the operation to be performed. when set to logic 1 a read is selected, while a logic 0 selects a write operation. figure 4 : device address control register following the successful acknowledgement of the slave address, the bus master sends a byte to th e PI4MSD5V9547 which is stored in the control register. if multiple bytes are received by the PI4MSD5V9547 , it saves the last byte received. this register can be written and read via the i2c - bus. figure 5 : control register control register definition a scx/sdx downstream pair, or channel, is selected by the contents of the control register. this register is written after the PI4MSD5V9547 has been addressed. the 4 lsbs of the control byte are used to determine which channel is to be selected. when a ch annel is selected, the channel will become active after a stop condition has been placed on the i2c - bus. this ensures that all scx/sdx lines will be in a high state when the channel is made active, so that no false conditions are generated at the time of c onnection.
|||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 4 0 pt054 4 - 2 8 / 1 8 /1 5 8 pi4 msd5v954 7 8 channel i2c bus multiplexer with reset control register d7 d6 d5 d4 b3 b2 b1 b0 command x x x x 0 x x x no channel selected x x x x 1 0 0 0 channel 0 enabled x x x x 1 0 0 1 channel 1 enabled x x x x 1 0 1 0 channel 2 enabled x x x x 1 0 1 1 channel 3 enabled x x x x 1 1 0 0 channel 4 enabled x x x x 1 1 0 1 channel 5 enabled x x x x 1 1 1 0 channel 6 enabled x x x x 1 1 1 1 channel 7 enabled 0 0 0 0 1 0 0 0 channel 0 enabled; power - up/reset default state control register: write channel selection; read channel stat us power - on reset when power is applied to vcc , an internal power - on reset (por) holds the PI4MSD5V9547 in a reset condition until vcc has reached vpor. at this point, the reset condition is released and the PI4MSD5V9547 registers and i2c - bus state machin e are initialized to their default states (all zeroes), causing all the channels to be deselected. thereafter, vcc must be lowered below 0.2 v for at least 5 u s in order to reset the device. the r eset input the reset input is an active low signal which m ay be us ed to recover from a bus fault condition. by asserting this signal low for a minimum of tw( rst)l, the PI4MSD5V9547 will reset its register and i2c - bus state machine and will deselect all channels. the reset input must be connected to v cc through a pull - up resistor.
|||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 4 0 pt054 4 - 2 8 / 1 8 /1 5 9 pi4 msd5v954 7 8 channel i2c bus multiplexer with reset voltage translation the pass gate transistors of the PI4MSD5V9547 are constructe d such that the vcc voltage can be used to limit the maximum voltage that is passed from one i2c - bus to another. figure 6 : vpass voltage vs vcc figure 6 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in section dc electrical characteristics of this data sheet). in order for the PI4MSD5V9547 to act as a voltage translator, the v pass voltage should be equal to, or lower than the lowest bus voltage. fo r example, if the main bus was running at 5 v, and the downstream buses were 3.3 v and 2.7 v, then v pass should be equal to or below 2.7 v to clamp the downstream bus voltages effec tively. looking at figure 6 , we see that v pass (max) is at 2.7 v when the PI4MSD5V9547 supply voltage is 3.5 v or lower so the PI4MSD5V9547 supply voltage could be set to 3.3 v. pull - up resistors can then be used to bring the bus voltages to their appropr iate levels i2c bus the i2c - bus is for 2 - way, 2 - line communication between dif ferent ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull - up resistor when c onnected to the output stages of a device. data transfer may be initiated only when the bus is not busy. one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes i n the data line at this time are interpreted as control signals figure 7 : bit transfer
|||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 4 0 pt054 4 - 2 8 / 1 8 /1 5 10 pi4 msd5v954 7 8 channel i2c bus multiplexer with reset both data and clock lines remain high when the bus is not busy. a high - to - low transition of the data line while the clock is high is defined as the start condit ion (s). a low - to - high transition of the data line while the clock is high is defined as the stop condition (p) figure 8 . definition of start and stop conditions a device generating a message is a transmitter, a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves figure 9 . system configuration the number of data bytes transferred between the start and the stop conditions from transmitter to receiv er is not limited. each byte of 8 bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed mus t generate an acknowledge after the reception of each byte. also, a master must generate an acknowledge after the reception of each byte t hat has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during t he acknowledge clock pulse so that the sda line is stable low during the high period of the acknowledge relat ed clock pulse; set - up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enabl e the master to generate a stop condition. figure 10 . acknowledgment on i2c bus
|||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 4 0 pt054 4 - 2 8 / 1 8 /1 5 11 pi4 msd5v954 7 8 channel i2c bus multiplexer with reset data is transmitted to the p i4msd5v9547 control regist er using the write mode shown in bellow figure 11 . write control register data is transmitted to the PI4MSD5V9547 control register using the write mode shown in bellow figure 1 2 . read control register
|||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 4 0 pt054 4 - 2 8 / 1 8 /1 5 12 pi4 msd5v954 7 8 channel i2c bus multiplexer with reset mechanical information ts sop - 24 ( l )
|||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 4 0 pt054 4 - 2 8 / 1 8 /1 5 13 pi4 msd5v954 7 8 channel i2c bus multiplexer with reset tqfn - 24 (zd) ordering information part no. package code package PI4MSD5V9547 le l 24 - pin, 173 mil wide ts sop PI4MSD5V9547 lex l 24 - pin, 173 mil wide ts sop , tape &reel PI4MSD5V9547zd ex zd 24 - pin, thine fine pitch quad f lat no - load(tqfn), tape &reel note: ? e = pb - free and green ? adding x suffix = tape /r eel pericom semiconductor corporation ? 1 - 800 - 435 - 2336 ? www.pericom.com pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. pericom does not assume any responsibility for use of any circuitry described other than the circu itry embodied in pericom pro duct. the company makes no representations that circuitry described herein is free from patent infringement or other rights, of pericom .

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